Within the last couple years I have started to become familiar with the RISC-V architecture. I still consider myself to be a "greenhorn" when it comes to computer hardware but it fascinates me none-the-less to consider how software meets the hardware layer. So when I had learned that RISC-V was an open source CPU architecture and was experiencing wide adoption across academia, I really started to pay attention. I strongly believe in, and have benefited from, open source software so I wanted to see what a open source hardware platform might look like.
When you discuss RISC-V you need to understand the competition, which in my eyes is primarily ARM and x86. ARM is the currently dominant RISC architecture popular on mobile devices and beginning to see desktop adoption. x86 is the currently dominant CISC architecture popular on desktops and servers. RISC-V does not imply any performance benefit compared to the existing architectures so why would one choose RISC-V over the established standards?
The real benefits of RISC-V are that it is open source (and therefore devoid of licensing fees) as well as being freely extensible and devoid of legacy baggage. These facts combined with its large scale adoption in academia is going to push RISC-V into the spotlight in the near future in my opinion. That is why I have started learning RISC-V assembly and architecture, because mainstream RISC-V adoption is becoming a near certainty.
Open source hardware allows entry of smaller startups to the industry. When these firms, often competing on razer thin margins, are able to save the licensing costs of hardware as well as have complete access to the specifications and extensions they become more viable and can sustain early cash burn. Less monopolization of hardware will result in more competition, more jobs, and more options. The natural expectation is the consumer and software developers will benefit from this competition.
The extensibility of RISC-V is another big draw for the platform. Crypto, big data, video processing, and AI have brought significant demand for ASIC designs which could easily be adapted by a RISC-V extension. Additionally, GPU vendors are beginning to support this architecture in their on board processors with formal specifications being made. Being at the fore-front of this wave is going to greatly increase its market share in the near future. This will likely start a strong push for processor standardization which will trickle over to mainstream CPUs as well.
RISC-V has the benefits of decades of CPU architecture design. It does not need to support any past mistakes or have significant layers of complexity for sake of backwards support. It is free to take all the best ideas of modern CPU architectures and put it into a well thought out package. This is where I see it having significant draw moving forward; if you want to start from scratch, knowing nothing of CPUs, you would probably want to start with the one that offers the least barrier to entry.
Which brings me to my final point regarding the adoption of RISC-V in academia. When students attend universities that have or cater specifically to RISC-V hardware in their curriculum, they are exposed to these technologies and may not even experience the alternatives. These are future generations which will want to work with these technologies in their professional settings. MIT is producing computer science alum that have written RISC-V operating systems, and these are the individuals that will be driving the technological decisions of future businesses.
I have a RISC-V SBC currently on backorder so I can graduate from RISC-V emulation on QEMU to real physical hardware. The demand for it is so hot I might have to wait a few more months for the production supply to catch up. Until then I just have to be patient and continue practicing my RISC-V assembly in an emulator.